oulib.h
00001
00018 #ifndef OULIB_INCLUDE
00019 #define OULIB_INCLUDE
00020
00021 #include <stdio.h>
00022 #include <avr/io.h>
00023 #include <util/delay.h>
00024 #include <avr/interrupt.h>
00025 #include <util/twi.h>
00026
00027 #define OULIB_VERSION "2012_02_14"
00028
00029 #ifndef F_CPU
00030 #error "F_CPU must be defined"
00031 #endif
00032
00033
00034
00035 #if (F_CPU == 160000UL)
00036 #define MS_SHIFT 4
00037 #define MS_GATE 0x0f
00038 #undef F_CPU
00039 #define F_CPU 16000000
00040 #elif (F_CPU == 16000000)
00041 #define MS_SHIFT 4
00042 #define MS_GATE 0x0f
00043 #elif (F_CPU == 8000000)
00044 #define MS_SHIFT 5
00045 #define MS_GATE 0x1f
00046 #elif (F_CPU == 1000000)
00047 #define MS_SHIFT 8
00048 #define MS_GATE 0xff
00049 #else
00050 #error "Bad F_CPU specification"
00051 #endif
00052
00053
00054 #ifdef atmega168
00055 # define TCCR0 TCCR0B
00056 # define TCCR2 TCCR2B
00057 # define UCSRA UCSR0A
00058 # define UCSRB UCSR0B
00059 # define UDR UDR0
00060 # define UDRE UDRE0
00061 # define RXC RXC0
00062 # define RXEN RXEN0
00063 # define TXEN TXEN0
00064 # define UBRRH UBRR0H
00065 # define UBRRL UBRR0L
00066 # define TICIE1 ICIE1
00067 # define RXCIE RXCIE0
00068 # define UDRIE UDRIE0
00069
00070 #define CPU_DEFINED
00071 #endif
00072
00073 #ifdef at90usb1287
00074 # define TCCR0 TCCR0B
00075 # define TCCR2 TCCR2B
00076 # define UCSRA UCSR1A
00077 # define UCSRB UCSR1B
00078
00079 # define UDR UDR1
00080 # define UDRE UDRE1
00081 # define RXC RXC1
00082 # define RXEN RXEN1
00083 # define TXEN TXEN1
00084 # define UBRRH UBRR1H
00085 # define UBRRL UBRR1L
00086
00087 # define RXCIE RXCIE1
00088 # define UDRIE UDRIE1
00089
00090 #define USART_RXC_vect USART1_RX_vect
00091 #define USART_UDRE_vect USART1_UDRE_vect
00092 #define CPU_DEFINED
00093 #endif
00094
00095 #ifdef atmega644p
00096 # define TCCR0 TCCR0B
00097 # define TCCR2 TCCR2B
00098 # define UCSRA UCSR0A
00099 # define UCSRB UCSR0B
00100 # define UDR UDR0
00101 # define UDRE UDRE0
00102 # define RXC RXC0
00103 # define RXEN RXEN0
00104 # define TXEN TXEN0
00105 # define UBRRH UBRR0H
00106 # define UBRRL UBRR0L
00107
00108
00109
00110 #define SERIAL_NPORTS_2
00111 #define CPU_DEFINED
00112 #endif
00113
00114 #ifdef atmega2560
00115 # define TCCR0 TCCR0B
00116 # define TCCR2 TCCR2B
00117 # define UCSRA UCSR0A
00118 # define UCSRB UCSR0B
00119 # define UDR UDR0
00120 # define UDRE UDRE0
00121 # define RXC RXC0
00122 # define RXEN RXEN0
00123 # define TXEN TXEN0
00124 # define UBRRH UBRR0H
00125 # define UBRRL UBRR0L
00126 # define RXCIE RXCIE0
00127 # define UDRIE UDRIE0
00128
00129
00130
00131 #define SERIAL_NPORTS_4
00132 #define TIMER1B
00133 #define TIMER1C
00134 #define CPU_DEFINED
00135 #define TIMER3
00136 #define TIMER4
00137 #define TIMER5
00138 #define ADC_CHANS_16
00139 #define HAS_PORTA
00140 #define HAS_PORTE
00141 #define HAS_PORTF
00142 #define HAS_PORTG
00143 #define HAS_PORTH
00144 #define HAS_PORTJ
00145 #define HAS_PORTK
00146 #endif
00147
00148
00149 #ifdef atmega8
00150 #define UCSR0B UCSRB
00151 #define UDRIE0 UDRIE
00152 #define RXCIE0 RXCIE
00153
00154 #define CPU_DEFINED
00155 #endif
00156
00157 #ifdef atmega88
00158 #define CPU_DEFINED
00159 #endif
00160
00161 #ifndef CPU_DEFINED
00162 #error "Missing definitions: CDEFS = -DF_CPU=16000000 -D$(MCU)"
00163 #endif
00164
00166
00170 struct OU_FILE {
00172 uint8_t port;
00173 };
00174
00181 struct OU_FILE_BUF {
00183 uint8_t port;
00185 uint8_t buf_size_in;
00187 uint8_t buf_size_out;
00189 volatile uint8_t buf_in_front;
00191 volatile uint8_t buf_in_back;
00193 volatile uint8_t buf_out_front;
00195 volatile uint8_t buf_out_back;
00197 char *buffer;
00198 };
00199
00200
00201
00202
00203 #ifndef SERIAL_NPORTS_2
00204 #ifndef SERIAL_NPORTS_4
00205 extern struct OU_FILE_BUF *ou_file_buf[1];
00206 #else
00207 extern struct OU_FILE_BUF *ou_file_buf[4];
00208 #endif
00209 #else
00210 extern struct OU_FILE_BUF *ou_file_buf[2];
00211 #endif
00212
00213
00215
00224 inline void serial0_receive_enable(void) {
00225 UCSRB |= _BV(RXCIE);
00226 }
00227
00228
00237 inline void serial0_receive_disable(void) {
00238 UCSRB &= ~_BV(RXCIE);
00239 }
00240
00249 inline void serial0_transmit_enable(void) {
00250 UCSRB |= _BV(UDRIE);
00251 }
00252
00261 inline void serial0_transmit_disable(void) {
00262 UCSRB &= ~_BV(UDRIE);
00263 }
00264
00265
00266 #if defined(SERIAL_NPORTS_2) || defined(SERIAL_NPORTS_4)
00267
00277 inline void serial1_receive_enable(void) {
00278 UCSR1B |= _BV(RXCIE1);
00279 }
00280
00291 inline void serial1_receive_disable(void) {
00292 UCSR1B &= ~_BV(RXCIE1);
00293 }
00294
00295
00306 inline void serial1_transmit_enable(void) {
00307 UCSR1B |= _BV(UDRIE1);
00308 }
00309
00320 inline void serial1_transmit_disable(void) {
00321 UCSR1B &= ~_BV(UDRIE1);
00322 }
00323 #endif
00324
00325
00326 #if defined(SERIAL_NPORTS_4)
00327
00338 inline void serial2_transmit_enable(void) {
00339 UCSR2B |= _BV(UDRIE2);
00340 }
00341
00352 inline void serial2_transmit_disable(void) {
00353 UCSR2B &= ~_BV(UDRIE2);
00354 }
00355
00366 inline void serial3_transmit_enable(void) {
00367 UCSR3B |= _BV(UDRIE3);
00368 }
00369
00380 inline void serial3_transmit_disable(void) {
00381 UCSR3B &= ~_BV(UDRIE3);
00382 }
00383
00394 inline void serial2_receive_enable(void) {
00395 UCSR2B |= _BV(RXCIE2);
00396 }
00397
00408 inline void serial2_receive_disable(void) {
00409 UCSR2B &= ~_BV(RXCIE2);
00410 }
00411
00422 inline void serial3_receive_enable(void) {
00423 UCSR3B |= _BV(RXCIE3);
00424 }
00425
00436 inline void serial3_receive_disable(void) {
00437 UCSR3B &= ~_BV(RXCIE3);
00438 }
00439
00440 #endif
00441
00442
00444
00445
00446 extern void delay_ms(unsigned int);
00447 extern void delay_us(unsigned int);
00448
00450
00451 extern void timer0_config(uint8_t config);
00452
00453
00454
00455 #define TIMER0_NOCLK 0
00456 #define TIMER0_NOPRE 1
00457 #define TIMER0_PRE_8 2
00458 #define TIMER0_PRE_64 3
00459 #define TIMER0_PRE_256 4
00460 #define TIMER0_PRE_1024 5
00461 #define TIMER0_EXT_FALLING 6
00462 #define TIMER0_EXT_RISING 7
00463
00464
00465
00466
00467
00468
00470
00471 extern void timer1_config(uint8_t config);
00472
00473 #define TIMER1_NOCLK 0
00474 #define TIMER1_NOPRE 1
00475 #define TIMER1_PRE_8 2
00476 #define TIMER1_PRE_64 3
00477 #define TIMER1_PRE_256 4
00478 #define TIMER1_PRE_1024 5
00479 #define TIMER1_EXT_FALLING 6
00480 #define TIMER1_EXT_RISING 7
00481
00482
00483
00484
00485
00486 extern uint16_t timer1_read(void);
00487 extern void timer1_set(uint16_t);
00488
00489 extern void timer1_output_compare_config(uint8_t config);
00490
00491 #define TIMER1_OUTPUT_COMPARE_CONFIG_NORMAL 0x0
00492 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_08 0x1
00493 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_09 0x2
00494 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_10 0x3
00495 #define TIMER1_OUTPUT_COMPARE_CONFIG_CTC_OCR1A 0x4
00496 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_08 0x5
00497 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_09 0x6
00498 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_10 0x7
00499 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PFC_ICR1 0x8
00500 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PFC_OCR1A 0x9
00501 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_ICR1 0xa
00502 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_OCR1A 0xb
00503 #define TIMER1_OUTPUT_COMPARE_CONFIG_CTC_ICR1 0xc
00504 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_ICR1 0xe
00505 #define TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_OCR1A 0xf
00506
00507
00508 extern void timer1_output_compare_A_set(uint16_t val);
00509 extern uint16_t timer1_output_compare_A_read(void);
00510
00511 extern void timer1_compare_output_A_mode_set(uint8_t mode);
00512
00513
00514 #define TIMER16B_COMPARE_OUTPUT_MODE_NORMAL 0
00515 #define TIMER16B_COMPARE_OUTPUT_MODE_TOGGLE 1
00516 #define TIMER16B_COMPARE_OUTPUT_MODE_CLEAR 2
00517 #define TIMER16B_COMPARE_OUTPUT_MODE_SET 3
00518
00519 #ifdef TIMER1B
00520 extern void timer1_output_compare_B_set(uint16_t val);
00521 extern uint16_t timer1_output_compare_B_read(void);
00522 extern void timer1_compare_output_B_mode_set(uint8_t mode);
00523 #endif
00524
00525 #ifdef TIMER1C
00526 extern void timer1_output_compare_C_set(uint16_t val);
00527 extern uint16_t timer1_output_compare_C_read(void);
00528 extern void timer1_compare_output_C_mode_set(uint8_t mode);
00529 #endif
00530
00531
00532
00533
00535
00536 extern void timer2_config(uint8_t config);
00537
00538
00539 #define TIMER2_NOCLK 0
00540 #define TIMER2_NOPRE 1
00541 #define TIMER2_PRE_8 2
00542 #define TIMER2_PRE_32 3
00543 #define TIMER2_PRE_64 4
00544 #define TIMER2_PRE_128 5
00545 #define TIMER2_PRE_256 6
00546 #define TIMER2_PRE_1024 7
00547
00549
00550 #ifdef TIMER3
00551 extern void timer3_config(uint8_t config);
00552
00553 #define TIMER3_NOCLK 0
00554 #define TIMER3_NOPRE 1
00555 #define TIMER3_PRE_8 2
00556 #define TIMER3_PRE_64 3
00557 #define TIMER3_PRE_256 4
00558 #define TIMER3_PRE_1024 5
00559 #define TIMER3_EXT_FALLING 6
00560 #define TIMER3_EXT_RISING 7
00561
00562 extern uint16_t timer3_read(void);
00563 extern void timer3_set(uint16_t);
00564
00565 extern void timer3_output_compare_config(uint8_t config);
00566
00567 #define TIMER3_OUTPUT_COMPARE_CONFIG_NORMAL 0x0
00568 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_PC_08 0x1
00569 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_PC_09 0x2
00570 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_PC_10 0x3
00571 #define TIMER3_OUTPUT_COMPARE_CONFIG_CTC_OCR1A 0x4
00572 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_F_08 0x5
00573 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_F_09 0x6
00574 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_F_10 0x7
00575 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_PFC_ICR1 0x8
00576 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_PFC_OCR1A 0x9
00577 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_PC_ICR1 0xa
00578 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_PC_OCR1A 0xb
00579 #define TIMER3_OUTPUT_COMPARE_CONFIG_CTC_ICR1 0xc
00580 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_F_ICR1 0xe
00581 #define TIMER3_OUTPUT_COMPARE_CONFIG_PWM_F_OCR1A 0xf
00582
00583
00584 extern void timer3_output_compare_A_set(uint16_t val);
00585 extern uint16_t timer3_output_compare_A_read(void);
00586 extern void timer3_compare_output_A_mode_set(uint8_t mode);
00587
00588 extern void timer3_output_compare_B_set(uint16_t val);
00589 extern uint16_t timer3_output_compare_B_read(void);
00590 extern void timer3_compare_output_B_mode_set(uint8_t mode);
00591
00592 extern void timer3_output_compare_C_set(uint16_t val);
00593 extern uint16_t timer3_output_compare_C_read(void);
00594 extern void timer3_compare_output_C_mode_set(uint8_t mode);
00595
00603 inline void timer3_enable(void) {
00604 TIMSK3 |= _BV(TOIE3);
00605 };
00606
00614 inline void timer3_disable(void) {
00615
00616 TIMSK3 &= ~_BV(TOIE3);
00617 };
00618
00619
00620 #endif
00621
00622
00624
00625 #ifdef TIMER4
00626 extern void timer4_config(uint8_t config);
00627
00628 #define TIMER4_NOCLK 0
00629 #define TIMER4_NOPRE 1
00630 #define TIMER4_PRE_8 2
00631 #define TIMER4_PRE_64 3
00632 #define TIMER4_PRE_256 4
00633 #define TIMER4_PRE_1024 5
00634 #define TIMER4_EXT_FALLING 6
00635 #define TIMER4_EXT_RISING 7
00636
00637 extern uint16_t timer4_read(void);
00638 extern void timer4_set(uint16_t);
00639
00640 extern void timer4_output_compare_config(uint8_t config);
00641
00642 #define TIMER4_OUTPUT_COMPARE_CONFIG_NORMAL 0x0
00643 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_PC_08 0x1
00644 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_PC_09 0x2
00645 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_PC_10 0x3
00646 #define TIMER4_OUTPUT_COMPARE_CONFIG_CTC_OCR1A 0x4
00647 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_F_08 0x5
00648 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_F_09 0x6
00649 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_F_10 0x7
00650 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_PFC_ICR1 0x8
00651 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_PFC_OCR1A 0x9
00652 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_PC_ICR1 0xa
00653 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_PC_OCR1A 0xb
00654 #define TIMER4_OUTPUT_COMPARE_CONFIG_CTC_ICR1 0xc
00655 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_F_ICR1 0xe
00656 #define TIMER4_OUTPUT_COMPARE_CONFIG_PWM_F_OCR1A 0xf
00657
00658
00659 extern void timer4_output_compare_A_set(uint16_t val);
00660 extern uint16_t timer4_output_compare_A_read(void);
00661 extern void timer4_compare_output_A_mode_set(uint8_t mode);
00662
00663 extern void timer4_output_compare_B_set(uint16_t val);
00664 extern uint16_t timer4_output_compare_B_read(void);
00665 extern void timer4_compare_output_B_mode_set(uint8_t mode);
00666
00667 extern void timer4_output_compare_C_set(uint16_t val);
00668 extern uint16_t timer4_output_compare_C_read(void);
00669 extern void timer4_compare_output_C_mode_set(uint8_t mode);
00670
00678 inline void timer4_enable(void) {
00679 TIMSK4 |= _BV(TOIE4);
00680 };
00681
00689 inline void timer4_disable(void) {
00690
00691 TIMSK4 &= ~_BV(TOIE4);
00692 };
00693
00694
00695 #endif
00696
00697
00699
00700 #ifdef TIMER5
00701 extern void timer5_config(uint8_t config);
00702
00703 #define TIMER5_NOCLK 0
00704 #define TIMER5_NOPRE 1
00705 #define TIMER5_PRE_8 2
00706 #define TIMER5_PRE_64 3
00707 #define TIMER5_PRE_256 4
00708 #define TIMER5_PRE_1024 5
00709 #define TIMER5_EXT_FALLING 6
00710 #define TIMER5_EXT_RISING 7
00711
00712 extern uint16_t timer5_read(void);
00713 extern void timer5_set(uint16_t);
00714
00715 extern void timer5_output_compare_config(uint8_t config);
00716
00717 #define TIMER5_OUTPUT_COMPARE_CONFIG_NORMAL 0x0
00718 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_PC_08 0x1
00719 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_PC_09 0x2
00720 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_PC_10 0x3
00721 #define TIMER5_OUTPUT_COMPARE_CONFIG_CTC_OCR1A 0x4
00722 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_F_08 0x5
00723 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_F_09 0x6
00724 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_F_10 0x7
00725 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_PFC_ICR1 0x8
00726 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_PFC_OCR1A 0x9
00727 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_PC_ICR1 0xa
00728 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_PC_OCR1A 0xb
00729 #define TIMER5_OUTPUT_COMPARE_CONFIG_CTC_ICR1 0xc
00730 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_F_ICR1 0xe
00731 #define TIMER5_OUTPUT_COMPARE_CONFIG_PWM_F_OCR1A 0xf
00732
00733
00734 extern void timer5_output_compare_A_set(uint16_t val);
00735 extern uint16_t timer5_output_compare_A_read(void);
00736 extern void timer5_compare_output_A_mode_set(uint8_t mode);
00737
00738 extern void timer5_output_compare_B_set(uint16_t val);
00739 extern uint16_t timer5_output_compare_B_read(void);
00740 extern void timer5_compare_output_B_mode_set(uint8_t mode);
00741
00742 extern void timer5_output_compare_C_set(uint16_t val);
00743 extern uint16_t timer5_output_compare_C_read(void);
00744 extern void timer5_compare_output_C_mode_set(uint8_t mode);
00745
00753 inline void timer5_enable(void) {
00754 TIMSK5 |= _BV(TOIE5);
00755 };
00756
00764 inline void timer5_disable(void) {
00765
00766 TIMSK5 &= ~_BV(TOIE5);
00767 };
00768
00769
00770 #endif
00771
00772
00773
00775
00776
00777
00778
00779
00780 extern FILE* serial_init_buffered(uint8_t port, unsigned long baud_rate,
00781 uint8_t buf_size_in, uint8_t buf_size_out);
00782
00783 extern int8_t serial_buffered_input_waiting(FILE *fp);
00784 extern int16_t serial_buffered_output_free(FILE* fp);
00785 extern int16_t serial_buffered_input_nbytes(FILE* fp);
00786 extern void serial_receive_isr(struct OU_FILE_BUF *fp);
00787 extern void serial_transmit_isr(struct OU_FILE_BUF *fp);
00788
00790
00791
00792 extern void adc_set_reference(uint8_t ref);
00793
00794 #define ADC_REF_AREF 0x0
00795 #define ADC_REF_AREF_CAP 0x1
00796 #define ADC_REF_2p56V 0x3
00797
00798 extern void adc_set_adlar(uint8_t adlar);
00799
00800 #define ADC_ADLAR_RIGHT 0
00801 #define ADC_ADLAR_LEFT 1
00802
00803
00804 extern void adc_set_channel(uint8_t chan);
00805
00806
00807 #ifdef atmega8
00808 #define ADC_CHANNEL_0 0x0
00809 #define ADC_CHANNEL_1 0x1
00810 #define ADC_CHANNEL_2 0x2
00811 #define ADC_CHANNEL_3 0x3
00812 #define ADC_CHANNEL_4 0x4
00813 #define ADC_CHANNEL_5 0x5
00814 #define ADC_CHANNEL_6 0x6
00815 #define ADC_CHANNEL_7 0x7
00816 #define ADC_CHANNEL_1p23V 0xE
00817 #define ADC_CHANNEL_0V 0xF
00818 #else
00819 #define ADC_CHANNEL_0 0x0
00820 #define ADC_CHANNEL_1 0x1
00821 #define ADC_CHANNEL_2 0x2
00822 #define ADC_CHANNEL_3 0x3
00823 #define ADC_CHANNEL_4 0x4
00824 #define ADC_CHANNEL_5 0x5
00825 #define ADC_CHANNEL_6 0x6
00826 #define ADC_CHANNEL_7 0x7
00827 #define ADC_CHANNEL_1p1V 0xE
00828 #define ADC_CHANNEL_0V 0xF
00829 #endif
00830
00831 #ifdef ADC_CHANS_16
00832 #define ADC_CHANNEL_8 0x20
00833 #define ADC_CHANNEL_9 0x21
00834 #define ADC_CHANNEL_10 0x22
00835 #define ADC_CHANNEL_11 0x23
00836 #define ADC_CHANNEL_12 0x24
00837 #define ADC_CHANNEL_13 0x25
00838 #define ADC_CHANNEL_14 0x26
00839 #define ADC_CHANNEL_15 0x27
00840 #endif
00841
00842 extern void adc_set_enable(uint8_t cmd);
00843 #define ADC_ENABLE 1
00844 #define ADC_DISABLE 0
00845
00857 inline void adc_start_conversion(void)
00858 {
00859 ADCSRA = ADCSRA | 0x40;
00860 }
00861
00875 inline uint8_t adc_interrupt_flag(void)
00876 {
00877 return((ADCSRA&0x10) >> 4);
00878 };
00879
00880 extern void adc_set_auto_trigger(uint8_t cmd);
00881 #define ADC_AUTO_TRIGGER_ENABLE 1
00882 #define ADC_AUTO_TRIGGER_DISABLE 0
00883
00884 extern void adc_interrupt_enable(uint8_t cmd);
00885 #define ADC_INTERRUPT_ENABLE 1
00886 #define ADC_INTERRUPT_DISABLE 0
00887
00888 extern void adc_set_prescalar(uint8_t cmd);
00889 #define ADC_PRESCALAR_2 0 // Correct? docs say this is factor 2 ***
00890
00891 #define ADC_PRESCALAR_4 2
00892 #define ADC_PRESCALAR_8 3
00893 #define ADC_PRESCALAR_16 4
00894 #define ADC_PRESCALAR_32 5
00895 #define ADC_PRESCALAR_64 6
00896 #define ADC_PRESCALAR_128 7
00897
00898 extern uint16_t adc_read(void);
00899
00900 #ifdef atmega88
00901 extern void adc_set_trigger_source(uint8_t cmd);
00902 #define ADC_TRIGGER_MODE_FREE 0x0
00903 #define ADC_TRIGGER_MODE_ACOMP 0x1
00904 #define ADC_TRIGGER_MODE_EXTINT 0x2
00905 #define ADC_TRIGGER_MODE_TC0A 0x3
00906 #define ADC_TRIGGER_MODE_TC0O 0x4
00907 #define ADC_TRIGGER_MODE_TC1B 0x5
00908 #define ADC_TRIGGER_MODE_TC1O 0x6
00909 #define ADC_TRIGGER_MODE_TCCE 0x7
00910 #define TIMSK_SINGLE
00911 #define CPU_DEFINED
00912
00913 extern void adc_set_digital_disable(uint8_t cmd);
00914 #endif
00915
00916 #ifdef atmega8
00917 #define TIMSK_SINGLE
00918 #define CPU_DEFINED
00919 #endif
00920
00921
00923
00924
00925 #define TWI_INTERRUPT_ENABLE (_BV(TWIE))
00926 #define TWI_INTERRUPT_DISABLE 0
00927
00928
00929
00930 extern void twi_send_start(void);
00931 extern void twi_wait_twint(void);
00932 extern void twi_send_byte(uint8_t val);
00933 extern void twi_send_stop(void);
00934 extern void twi_interrupt_config(uint8_t cmd);
00935 extern void twi_set_prescalar(uint8_t pre);
00936 #define TWI_PRESCALAR_1 0
00937 #define TWI_PRESCALAR_4 (_BV(TWPS0))
00938 #define TWI_PRESCALAR_16 (_BV(TWPS1))
00939 #define TWI_PRESCALAR_64 (_BV(TWPS0) | _BV(TWPS1))
00940
00941 extern void twi_set_ack(uint8_t ack);
00942 #define TWI_ACKNOWLEDGE_ENABLE (_BV(TWEA))
00943 #define TWI_ACKNOWLEDGE_DISABLE 0
00944
00946
00947
00955 inline void timer0_enable(void) {
00956 #ifdef TIMSK_SINGLE
00957 TIMSK |= _BV(TOIE0);
00958 #else
00959
00960 TIMSK0 |= _BV(TOIE0);
00961 #endif
00962
00963 };
00964
00973 inline void timer0_disable(void) {
00974 #ifdef TIMSK_SINGLE
00975 TIMSK &= ~_BV(TOIE0);
00976 #else
00977 TIMSK0 &= ~_BV(TOIE0);
00978 #endif
00979 };
00980
00991 inline uint8_t timer0_read(void) {
00992 return(TCNT0);
00993 };
00994
01004 inline void timer0_set(uint8_t val) {
01005 TCNT0 = val;
01006 };
01007
01008
01016 inline void timer1_enable(void) {
01017 #ifdef TIMSK_SINGLE
01018 TIMSK |= _BV(TOIE1);
01019 #else
01020 TIMSK1 |= _BV(TOIE1);
01021
01022 #endif
01023 };
01024
01032 inline void timer1_disable(void) {
01033
01034 #ifdef TIMSK_SINGLE
01035 TIMSK &= ~_BV(TOIE1);
01036 #else
01037 TIMSK1 &= ~_BV(TOIE1);
01038 #endif
01039 };
01040
01049 inline void timer1_output_compare_A_enable(void)
01050 {
01051 #ifdef TIMSK_SINGLE
01052 TIMSK |= _BV(OCIE1A);
01053 #else
01054 TIMSK1 |= _BV(OCIE1A);
01055
01056 #endif
01057 };
01058
01067 inline void timer1_output_compare_A_disable(void)
01068 {
01069 #ifdef TIMSK_SINGLE
01070 TIMSK &= ~_BV(OCIE1A);
01071 #else
01072 TIMSK1 &= ~_BV(OCIE1A);
01073
01074 #endif
01075 };
01076
01077
01085 inline void timer1_output_compare_B_enable(void)
01086 {
01087 #ifdef TIMSK_SINGLE
01088 TIMSK |= _BV(OCIE1B);
01089 #else
01090 TIMSK1 |= _BV(OCIE1B);
01091
01092 #endif
01093 };
01094
01103 inline void timer1_output_compare_B_disable(void)
01104 {
01105 #ifdef TIMSK_SINGLE
01106 TIMSK &= ~_BV(OCIE1B);
01107 #else
01108 TIMSK1 &= ~_BV(OCIE1B);
01109
01110 #endif
01111
01112 };
01113
01122 inline void timer2_enable(void) {
01123 #ifdef TIMSK_SINGLE
01124 TIMSK |= _BV(TOIE2);
01125 #else
01126 TIMSK2 |= _BV(TOIE2);
01127 #endif
01128 };
01129
01138 inline void timer2_disable(void) {
01139 #ifdef TIMSK_SINGLE
01140 TIMSK &= ~_BV(TOIE2);
01141 #else
01142 TIMSK2 &= ~_BV(TOIE2);
01143 #endif
01144 };
01145
01156 inline uint8_t timer2_read(void) {
01157 return(TCNT2);
01158 };
01159
01170 inline void timer2_set(uint8_t val) {
01171 TCNT2 = val;
01172 };
01173
01174
01176
01177
01189 inline uint8_t twi_get_twint(void)
01190 {
01191 return(TWCR & _BV(TWINT));
01192 };
01193
01194
01205 inline uint8_t twi_get_status(void)
01206 {
01207 return(TWSR & 0xf8);
01208 };
01209
01220 inline uint8_t twi_get_byte(void)
01221 {
01222 return(TWDR);
01223 };
01224
01235 inline void twi_set_state(uint8_t val)
01236 {
01237 TWCR = val;
01238 };
01239
01250 inline uint8_t twi_get_state(void)
01251 {
01252 return(TWCR);
01253 };
01254
01266 inline uint8_t twi_get_stop(void)
01267 {
01268 return(TWCR & _BV(TWSTO));
01269 };
01270
01282 inline void twi_set_rate(uint8_t rate)
01283 {
01284 TWBR = rate;
01285 }
01286
01298 inline void twi_set_address(uint8_t address)
01299 {
01300 TWAR = address;
01301 };
01302
01312 inline void twi_set_twint(void)
01313 {
01314 TWCR |= _BV(TWINT);
01315 };
01316
01317
01319
01328 #define spi_interrupt_enable() (SPCR |= _BV(SPIE))
01329
01338 #define spi_interrupt_disable() (SPCR &= ~_BV(SPIE))
01339
01348 #define spi_enable() (SPCR |= _BV(SPE))
01349
01358 #define spi_disable() (SPCR |= _BV(SPE))
01359
01368 #define spi_data_order_msb_first() (SPCR &= ~_BV(DORD))
01369
01377 #define spi_data_order_lsb_first() (SPCR |= _BV(DORD))
01378
01387 #define spi_mode_master() (SPCR |= _BV(MSTR))
01388
01397 #define spi_mode_slave() (SPCR &= ~_BV(MSTR))
01398
01407 #define spi_clock_idle_high() (SPCR |= _BV(CPOL))
01408
01417 #define spi_clock_idle_low() (SPCR &= ~_BV(CPOL))
01418
01427 #define spi_clock_sample_leading() (SPCR &= ~_BV(CPHA))
01428
01437 #define spi_clock_sample_trailing() (SPCR |= _BV(CPHA))
01438
01439
01440 #define SPI_PRE_2 4
01441 #define SPI_PRE_4 0
01442 #define SPI_PRE_8 5
01443 #define SPI_PRE_16 1
01444 #define SPI_PRE_32 6
01445 #define SPI_PRE_64 2
01446 #define SPI_PRE_64b 7
01447 #define SPI_PRE_128 3
01448
01449 extern void spi_prescale_config(uint8_t prescale);
01450
01451
01463 #define spi_write_collision_p() ((SPSR >> WCOL) & 0x1)
01464
01465
01466
01468
01469
01470 #endif
