Timer 1

Functions

void timer1_compare_output_A_mode_set (uint8_t mode)
void timer1_config (uint8_t config)
uint16_t timer1_output_compare_A_read (void)
void timer1_output_compare_A_set (uint16_t val)
void timer1_output_compare_config (uint8_t config)
uint16_t timer1_read (void)
void timer1_set (uint16_t val)
void timer1_enable (void)
void timer1_disable (void)
void timer1_output_compare_A_enable (void)
void timer1_output_compare_A_disable (void)
void timer1_output_compare_B_enable (void)
void timer1_output_compare_B_disable (void)

Function Documentation

void timer1_compare_output_A_mode_set ( uint8_t  mode  ) 

Configure the timer 1 compare output A mode.

Parameters:
mode One of:
TIMER16B_COMPARE_OUTPUT_MODE_NORMAL: Normal operation
TIMER16B_COMPARE_OUTPUT_MODE_TOGGLE: Toggle on output compare
TIMER16B_COMPARE_OUTPUT_MODE_CLEAR: Clear on output compare
TIMER16B_COMPARE_OUTPUT_MODE_SET: Set on output compare
Author:
Andrew H. Fagg
void timer1_config ( uint8_t  config  ) 

Determine the clock source for timer 1

Parameters:
config One of:
TIMER1_NOCLK: no input clock
TIMER1_NOPRE: No prescalar
TIMER1_PRE_8: Prescalar of 8
TIMER1_PRE_64: Prescalar of 64
TIMER1_PRE_256: Prescalar of 256
TIMER1_PRE_1024: Prescalar of 1024
TIMER1_EXT_FALLING: Count on falling edge of external pin T1
TIMER1_EXT_RISING: Count on rising edge of external pin T1
Author:
Andrew H. Fagg
void timer1_disable ( void   )  [inline]

Disable the timer 1 overflow interrupt.

Author:
Andrew H. Fagg
void timer1_enable ( void   )  [inline]

Enable the timer 1 overflow interrupt.

Author:
Andrew H. Fagg
void timer1_output_compare_A_disable ( void   )  [inline]

Disable the timer 1 output compare unit A interrupt.

Author:
Andrew H. Fagg
void timer1_output_compare_A_enable ( void   )  [inline]

Enable the timer 1 output compare unit A interrupt.

Author:
Andrew H. Fagg
uint16_t timer1_output_compare_A_read ( void   ) 

Read the state of the timer 1 output compare unit A register.

Note: this implementation is thread safe.

Returns:
The current state of the timer 1 output compare unit A register.
Author:
Andrew H. Fagg
void timer1_output_compare_A_set ( uint16_t  val  ) 

Set the state of the timer 1 output compare unit A register.

Note: this implementation is thread safe.

Parameters:
val The new value of the timer 1 output compare unit A register.
Author:
Andrew H. Fagg
void timer1_output_compare_B_disable ( void   )  [inline]

Disable the timer 1 output compare unit B interrupt.

Author:
Andrew H. Fagg
void timer1_output_compare_B_enable ( void   )  [inline]

Enable the timer 1 output compare unit B interrupt.

Author:
Andrew H. Fagg
void timer1_output_compare_config ( uint8_t  config  ) 

Configure the timer 1 output compare unit.

Parameters:
config One of:
TIMER1_OUTPUT_COMPARE_CONFIG_NORMAL: Normal operation
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_08: PWM, Phase Correct, 8-bit
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_09: PWM, Phase Correct, 9-bit
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_10: PWM, Phase Correct, 10-bit
TIMER1_OUTPUT_COMPARE_CONFIG_CTC_OCR1A: CTC, Top = OCRA1
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_08: Fast PWM, 8-bit
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_09: Fast PWM, 9-bit
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_10: Fast PWM, 10-bit
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PFC_ICR1: PWM, Phase and Frequency Correct, Top = ICR1
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PFC_OCR1A: PWM, Phase and Frequency Correct, Top = OCR1A
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_ICR1: PWM, Phase Correct, Top = ICR1
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_PC_OCR1A: PWM, Phase Correct, Top = OCR1A
TIMER1_OUTPUT_COMPARE_CONFIG_CTC_ICR1: CTC, Top = ICR1
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_ICR1: Fast PWM, Top = ICR1
TIMER1_OUTPUT_COMPARE_CONFIG_PWM_F_OCR1A: Fast PWM, Top = OCR1A
Author:
Andrew H. Fagg
uint16_t timer1_read ( void   ) 

Read the state of the timer 1 counter.

Note: this implementation is thread safe.

Returns:
The current state of the timer 1 counter
Author:
Andrew H. Fagg
void timer1_set ( uint16_t  val  ) 

Set the state of the timer 1 counter

Note: this implementation is thread safe.

Parameters:
val The new value of the timer 1 counter.
Author:
Andrew H. Fagg
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